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MAX8521ETP Rev. A
RELIABILITY REPORT FOR MAX8521ETP PLASTIC ENCAPSULATED DEVICES
June 29, 2003
MAXIM INTEGRATED PRODUCTS
120 SAN GABRIEL DR. SUNNYVALE, CA 94086
Written by
Reviewed by
Jim Pedicord Quality Assurance Reliability Lab Manager
Bryan J. Preeshl Quality Assurance Executive Director
Conclusion The MAX8521 successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxim's continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim's quality and reliability standards. Table of Contents I. ........Device Description II. ........Manufacturing Information III. .......Packaging Information V. ........Quality Assurance Information VI. .......Reliability Evaluation IV. .......Die Information .....Attachments
I. Device Description A. General The MAX8521 is designed to drive thermo-electric coolers (TECs) in space-constrained optical modules. The device delivers 1.5A output current and controls the TEC current to eliminate harmful current surges. On-chip FETs minimize external components and high switching frequency reduces the size of external components. The MAX8521 operates from a single supply and bias the TEC between the outputs of two synchronous buck regulators. This operation allows for temperature control without "dead zones" or other nonlinearities at low current. This arrangement ensures that the control system does not hunt when the set point is very close to the natural operating point, requiring a small amount of heating or cooling. An analog control signal precisely sets the TEC current. The device features accurate, individually adjustable heating current limit and cooling current limit, along with maximum TEC voltage limit to improve the reliability of optical modules. An analog output signal monitors the TEC current. A unique ripple cancellation scheme helps reduce noise. The MAX8521 is also available in a 5mm x 5mm thin QFN, as well as a space-saving 3mm x 3mm UCSPTM, with a pin-selectable switching frequency of 500kHz or 1MHz. B. Absolute Maximum Ratings Item VDD to GND SHDN, MAXV, MAXIP, MAXIN, CTLI to GND COMP, FREQ, OS1, OS2, CS, REF, ITEC to GND PVDD1, PVDD2 to GND PVDD1, PVDD2 to VDD PGND1, PGND2 to GND COMP, REF, ITEC Short to GND LX Current (Note 1) Maximum Junction Temperature Storage Temperature Range Lead Temperature (soldering 10s) Continuous Power Dissipation (TA = +70C) 20-Pin 5mm x 5mm x 0.9mm QFN (Note 2) Derates above +70C 20-Pin 5mm x 5mm x 0.9mm QFN (Note 2)
Rating -0.3V to +6V -0.3V to +6V -0.3V to (VDD + 0.3V) -0.3V to (VDD + 0.3V) -0.3V to +0.3V -0.3V to +0.3V Indefinite 2.25A LX Current +150C -65C to +150C +300C 1670mW 20.8mW/C
Note 1: LX has internal clamp diodes to PGND and PVDD. Applications that forward bias these diodes should take care not to exceed the IC's package power dissipation limits. Note 2: Solder underside metal slug to PC board ground plane.
II. Manufacturing Information A. Description/Function: B. Process: C. Number of Device Transistors: D. Fabrication Location: E. Assembly Location: F. Date of Initial Production: Smallest TEC Power Drivers for Optical Modules B8 (Standard 0.8 micron silicon gate CMOS) 3007 California, USA Thailand October, 2002
III. Packaging Information A. Package Type: B. Lead Frame: C. Lead Finish: D. Die Attach: E. Bondwire: F. Mold Material: G. Assembly Diagram: H. Flammability Rating: I. Classification of Moisture Sensitivity per JEDEC standard JESD22-112: 20-Pin QFN (5x5) Copper Solder Plate Silver-Filled Epoxy Gold (2.0 mil dia.) Epoxy with silica filler # 05-9000-0102 Class UL94-V0
Level 1
IV. Die Information A. Dimensions: B. Passivation: C. Interconnect: D. Backside Metallization: E. Minimum Metal Width: F. Minimum Metal Spacing: G. Bondpad Dimensions: H. Isolation Dielectric: I. Die Separation Method: 120 x 120 mils Si3N4/SiO2 (Silicon nitride/ Silicon dioxide) Aluminum/Si (Si = 1%) None 0.8 microns (as drawn) 0.8 microns (as drawn) 5 mil. Sq. SiO2 Wafer Saw
V. Quality Assurance Information A. Quality Assurance Contacts: Jim Pedicord (Reliability Lab Manager) Bryan Preeshl (Executive Director) Kenneth Huening (Vice President) 0.1% for all electrical parameters guaranteed by the Datasheet. 0.1% For all Visual Defects.
B. Outgoing Inspection Level:
C. Observed Outgoing Defect Rate: < 50 ppm D. Sampling Plan: Mil-Std-105D VI. Reliability Evaluation A. Accelerated Life Test The results of the 135C biased (static) life test are shown in Table 1. Using these results, the Failure Rate () is calculated as follows: = 1 = MTTF 1.83 192 x 4389 x 48 x 2 (Chi square value for MTTF upper limit)
Temperature Acceleration factor assuming an activation energy of 0.8eV = 22.62 x 10-9 = 22.62 F.I.T. (60% confidence level @ 25C)
This low failure rate represents data collected from Maxim's reliability monitor program. In addition to routine production Burn-In, Maxim pulls a sample from every fabrication process three times per week and subjects it to an extended Burn-In prior to shipment to ensure its reliability. The reliability control level for each lot to be shipped as standard product is 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece sample. Maxim performs failure analysis on any lot that exceeds this reliability control level. Attached Burn-In Schematic (Spec. # 06-6077) shows the static Burn-In circuit. Maxim also performs quarterly 1000 hour life test monitors. This data is published in the Product Reliability Report (RR-1M). B. Moisture Resistance Tests Maxim pulls pressure pot samples from every assembly process three times per week. Each lot sample must meet an LTPD = 20 or less before shipment as standard product. Additionally, the industry s tandard 85C/85%RH testing is done per generic device/package family once a quarter. C. E.S.D. and Latch-Up Testing The PM83-1 die type has been found to have all pins able to withstand a transient pulse of 1000V, per MilStd-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device withstands a current of 100mA.
Table 1 Reliability Evaluation Test Results MAX8521ETP TEST ITEM TEST CONDITION FAILURE IDENTIFICATION SAMPLE SIZE NUMBER OF FAILURES
PACKAGE
Static Life Test (Note 1) Ta = 135C Biased Time = 192 hrs. Moisture Testing (Note 2) Pressure Pot Ta = 121C P = 15 psi. RH= 100% Time = 168hrs. Ta = 85C RH = 85% Biased Time = 1000hrs.
DC Parameters & functionality
48
0
DC Parameters & functionality
QFN
77
0
85/85
DC Parameters & functionality
77
0
Mechanical Stress (Note 2) Temperature Cycle -65C/150C 1000 Cycles Method 1010 DC Parameters 77 0
Note 1: Life Test Data may represent plastic DIP qualification lots. Note 2: Generic Package/Process data
Attachment #1 TABLE II. Pin combination to be tested. 1/ 2/
Terminal A (Each pin individually connected to terminal A with the other floating) 1. 2. All pins except VPS1 3/ All input and output pins
Terminal B (The common combination of all like-named pins connected to terminal B) All VPS1 pins All other input-output pins
1/ Table II is restated in narrative form in 3.4 below. 2/ No connects are not to be tested. 3/ Repeat pin combination I for each named Power supply and for ground (e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc). 3.4 a. b. Pin combinations to be tested. Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal B. All pins except the one being tested and the ground pin(s) shall be open. Each pin individually connected to terminal A with respect to each different set of a combination of all named power supply pins (e.g., V , or V SS1 SS2 or V SS3 or V CC1 , or V CC2 ) connected to terminal B. All pins except the one being tested and the power supply pin or set of pins shall be open. Each input and each output individually connected to terminal A with respect to a combination of all the other input and output pins connected to terminal B. All pins except the input or output pin being tested and the combination of all the other input and output pins shall be open.
c.
TERMINAL C
R1 S1 R2
TERMINAL A REGULATED HIGH VOLTAGE SUPPLY
S2 C1
DUT SOCKET
SHORT CURRENT PROBE (NOTE 6)
TERMINAL B
R = 1.5k C = 100pf
TERMINAL D Mil Std 883D Method 3015.7 Notice 8
5x5x0.8 MM QFN THIN PKG.
EXPOSED PAD PKG.
ONCE PER SOCKET
ONCE PER BOARD
2.0Ohms (0.010W)
+5V
10 K (0.01W)
10 K (0.01W)
20
PVDD1
19
DS1
18
DS2
17
CS
16
PVDD2
1
LX1
LX2
15
2
PGND1
PGND2
14
3
SHDNB
FREQ
13
10 uF
10 uF
4 100K
COMP
VDD
12 100k
5
ITEC MAXIN MAXIP MAXV REF CTLI
GND
11
6
7
8
9
10
1 uF
100 K (0.01W)
DEVICES: MAX 8520 PACKAGE: 20-QFN MAX. EXPECTED CURRENT = 25mA
DOCUMENT I.D. 06-6077 REVISION A
DRAWN BY: TEK TAN NOTES:
MAXIM
TITLE: BI
Circuit (MAX8520)
PAGE
2
OF 3

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